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Keynote Lectures

PECCS is a joint conference composed of three concurrent conferences: PEC and SPCS. These three conferences are always co-located and held in parallel. Keynote lectures are plenary sessions and can be attended by all PECCS participants.

Programming Support for Future Parallel Architectures
Siegfried Benkner, University of Vienna, Austria

Cognitive Computing Meets the Pervasive Internet-of-Things
Maria R. Ebling, IBM T.J. Watson Research Center, United States

Tactile Internet Design Challenges-Network Perspective
Hamid Aghvami, King's College London, United Kingdom

Runtime Aware Architectures
Mateo Valero, Universidad Politecnica de Catalunya, Spain

 

Programming Support for Future Parallel Architectures

Siegfried Benkner
University of Vienna
Austria
 

Brief Bio
Siegfried Benkner is a professor of Computer Science and the head of the Scientific Computing Research Group at the University of Vienna, Austria. His research interests include languages, compilers and runtime systems for parallel and distributed systems, service-oriented software architectures, as well as Cloud computing and Big Data. A major current research focus is on programming support for heterogeneous parallel systems. Recently, Benkner’s group coordinated the European PEPPHER project (Programmability and Performance Portability of Heterogeneous Many-Core Systems) and was a partner in the European Autotune project (Automatic Online Tuning). Siegfried was involved in the organization of several international conferences and was program chair of ICPP 2009 and EuroMPI 2012. Siegfried Benkner has published more than 100 peer-reviewed publications and is a member of the ACM, the IEEE, and the HiPEAC Network of Excellence.


Abstract
Due to various physical constraints the performance of single processors has reached its limits, and all major hardware vendors switched to multi-core architectures. In addition, there is a trend towards heterogeneous parallel systems comprised of conventional multi-core CPUs, GPUs, and other types of accelerators. As a consequence, the development of applications that can exploit the full potential of emerging parallel systems is becoming more and more challenging. In this talk we outline the major challenges associated with software development for future parallel architectures, including higher-level parallel programming approaches, advanced runtime technology, and automatic performance tuning tools. In particular we will present a high-level compositional approach to parallel software development in concert with an intelligent runtime system and automatic performance tuning techniques. Such an approach can significantly enhance programmability of future parallel systems, while ensuring efficiency and performance portability across a range of different architectures. We report on recent results of two European research projects, which addressed the challenges of software development for current and emerging parallel systems, and discuss related research efforts and potential future directions.



 

 

Cognitive Computing Meets the Pervasive Internet-of-Things

Maria R. Ebling
IBM T.J. Watson Research Center
United States
 

Brief Bio

Maria Ebling is a Director at the IBM T. J. Watson Research Center. She manages a team building systems capable of supporting cognitive computing analytics, solutions, and environments while not forgetting about the people who have to use them. She received a B.S. from Harvey Mudd College and an M.S. and a Ph.D. in computer science from Carnegie Mellon University. Her interests are in distributed systems supporting cognitive computing, mobile and pervasive computing, privacy, and human-computer interaction. She serves as the Editor-in-Chief of IEEE Pervasive Computing. She is a member of the IBM Academy of Technology, a Distinguished Member of the ACM and a senior member of the IEEE.


Abstract
“The most profound technologies are those that disappear. They weave themselves into the fabric of everyday life.” –Mark Weiser

We have made much progress toward achieving the vision Mark Weiser put forward in his seminal Scientific American paper, “The Computer for the 21st Century.” Yet, we still see the tabs, pads and boards around us on a daily basis: these technologies have not disappeared, and they continue to demand our attention by bombarding us with notifications at the most inopportune moments. Our current technologies have not yet achieved Weiser’s vision of calm technology, of technology that rests in the periphery of our attention, rises to the center of our attention when appropriate, and later returns to the periphery when that need passes.  Cognitive systems will help us make progress in this important and elusive dimension. Cognitive systems have the potential to learn to recognize patterns in our behavior, our surroundings, our needs, and our desires. Their ability to “read” text, “see” images, and “hear” natural speech will prove to be keys in assisting us in our everyday activities. In this talk, I will present some of the many examples at the intersection among pervasive computing, the Internet-of-Things, and cognitive computing and will discuss how this intersection will draw us closer to Weiser’s vision.



 

 

Tactile Internet Design Challenges-Network Perspective

Hamid Aghvami
King's College London
United Kingdom
 

Brief Bio

Hamid Aghvami joined the academic staff at King’s in 1984. In 1989 he was promoted to Reader, and in 1993 was promoted Professor in Telecommunications Engineering. He was the Director of the Centre for Telecommunications Research at King’s from 1994 to 2014. 

Professor Aghvami carries out consulting work on Digital Radio Communications Systems for British and International companies; he has published over 550 technical journal and conference papers, and given invited talks and courses the world over on various aspects of Personal and Mobile Radio Communications. He was Visiting Professor at NTT Radio Communication Systems Laboratories in 1990, Senior Research Fellow at BT Laboratories in 1998-1999, and was an Executive Advisor to Wireless Facilities Inc., USA, in 1996-2002. He is the Chairman of Advanced Wireless Technology Group Ltd. He is also the Managing Director of Wireless Multimedia Communications Ltd, his own consultancy company. 

Professor Aghvami leads an active research team working on numerous mobile and personal communications projects for Fourth and fifth generation networks; these projects are supported both by government and industry. He was a member of the Board of Governors of the IEEE Communications Society in 2001-2003, was a Distinguished Lecturer of the IEEE Communications Society in 2004-2007, and has been member, Chairman, and Vice-Chairman of the technical programme and organising committees of a large number of international conferences. He is also founder of the International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC), a major yearly conference attracting some 1,000 attendees. 

Professor Aghvami was awarded the IEEE Technical Committee on Personal Communications (TCPC) Recognition Award in 2005 for his outstanding technical contributions to the communications field, and for his service to the scientific and engineering communities. Professor Aghvami is a Fellow of the Royal Academy of Engineering, Fellow of the IET, Fellow of the IEEE, and in 2009 was awarded a Fellowship of the Wireless World Research Forum in recognition of his personal contributions to the wireless world, and for his research achievements as Director at the Centre for Telecommunications Research at King’s.


Abstract
Haptic and control communications network (Tactile Internet) is a communication platform enabling touching, monitoring, controlling and steering objects (things) remotely to support a wide range of emerging and future applications in the vertical business sectors such as: health & care, transportation, manufacturing, entrainment & events, smart grid, finance and new emerging markets.
5G wireless will comprise a multiple of interworked heterogeneous radio access networks from evolution of current radio access networks to new ones (5G vision). A Haptic and control radio access network will be an essential and important element of 5G wireless-Phase 2 and future Tactile Internet. Most of Haptic and Control Communications applications such as remote surgery require a few millisecond (ms) round trip time (RTT) delay and a very high reliability (in the order of 99.9999%). Achieving such a low RTT delay and high reliability while keeping complexity at a minimum level is a highly complex task and can be considered the main challenge for future network researchers and designers. It is well known that the delay and low reliability cause instability in the local feedback loops in both ends (haptic and control systems) of the network.
This talk will address the challenges facing the network designers to achieve the above mentioned performance indicators for end-to-end connectivity and across all network protocol stack layers from physical layer through Medium Access Control (MAC), network and transport layers to application layer.



 

 

Runtime Aware Architectures

Mateo Valero
Universidad Politecnica de Catalunya
Spain
 

Brief Bio

Mateo Valero, http://www.bsc.es/cv-mateo/, obtained his Telecommunication Engineering Degree from the Technical University of Madrid (UPM) in 1974 and his Ph.D. in Telecommunications from the Technical University of Catalonia (UPC) in 1980. He is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and he has given more than 400 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.
Dr. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award 2007 by the IEEE and ACM; Seymour Cray Award 2015 by IEEE;  Harry Goode Award 2009 by IEEE: ACM Distinguished Service Award 2012; Euro-Par Achievement Award 2015; the Spanish National Julio Rey Pastor award, in recognition of research in Mathematics; the Spanish National Award “Leonardo Torres Quevedo” that recognizes research in engineering;  the “King Jaime I” in basic research given by Generalitat Valenciana; the  Research Award by the Catalan Foundation for Research and Innovation and the “Aragón Award” 2008  given by the Government of Aragón. He has been named Honorary Doctor by the University of Chalmers, by the University of Belgrade, by the Universities of Las Palmas de Gran Canaria, Zaragoza, Complutense de Madrid, Cantabria and Granada in Spain and by the University of Veracruz in Mexico.  "Hall of the Fame" member of the ICT European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon,November 2008); Honoured with Creu de Sant Jordi 2016 by Generalitat de Catalunya. It is the highest recognition granted by the Government.
In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected Correspondant Academic of the Spanish Royal Academy of Science, in 2006  member of the Royal Spanish Academy of Doctors, in 2008 member of the Academia Europaea and in 2012 Correspondant Academic of the Mexican Academy of Sciences. He is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow. 
In 1998 he won a “Favourite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him. 


Abstract
In the last years the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore's Law vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while computer architects proposed techniques to aggressively exploit Instruction-Level Parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors on a chip. While these designs are able to compensate the clock frequency stagnation, they face multiple problems in terms of power consumption, programmability, resilience or memory. The solution is to give more responsibility to the runtime system and to let it tightly collaborate with the hardware. The runtime has to drive the design of future multi-cores architectures. In this talk, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective.



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